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In this course, you will learn:
- Fundamentals of SystemVerilog for Verifying RTL
- Fundamentals of OOP for FPGA Engineers.
- Fundamentals of Constraint Random Verification Methodology.
- Fundamentals of Layered Testbench Architecture.
- Developing Generator, Driver, Monitor, Scoreboard, and Environment Classes.
- SV has arrays, queues, dynamic arrays, tasks, and methods.
- Interprocess communication and SV randomization.
Syllabus:
- IDE
- Fundamentals : Procedural Constructs
- Understading SV datatypes
- Verification Fundamentals
- Fundamentals of System Verilog OOP Construct
- Randomization
- IPC
- Getting Started with Interface
- SystemVerilog For Verification Part 2
