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In this course, you will:
- Learn about Assertions and Functional Coverage, as well as how to utilise the SystemVerilog language to implement them.
- Gain practical experience by following examples and homework.
- Add these vital abilities to your profile that are required for every Verification position in today's business.
Syllabus:
1. System Verilog Assertions - Basics and Sequences
- SVA Basics - Immediate and Concurrent Assertions
- SVA Basics - Sequence and Property Blocks
- SequenceOperators - Repeat Operators
- SequenceOperators - AND , OR
- SequenceOperators -FirstMatch, Throughout and Within
- SequenceOperators- if else, ended and triggered
- Sequences - Local Variables and Subroutines
- Sequences - Sampled Value Functions
- Sequences_SystemTasks_Functions
2. System Verilog Assertions - Properties and Clocking
- SVA - Properties - Basics and Types
- SVA - Recursive Properties
- Clock resolution and Multiple Clock sequences
- SVA - Binding and expect property
- SV Assertions - Tips and Best Usages
3. System Verilog Functional Coverage Coding
- SV Covergroups and Coverpoints - Basics
- Coverage bins - Auto, transition, wildcard, ignore, illegal
- SV Cross Coverage
- Coverage options and usages
- Coverage Methods, Performance, cover properties and misc
- SV Functoinal Coverage Lab Exercises
