SOC Verification using SystemVerilog

Description

In this course, you will :

• Learn about the key ideas in the SOC/ASIC/VLSI design verification flow.
• Learn how to use System Verilog for Functional Verification.
• Prepare for and be qualified for a Verification position in the semiconductor sector.
• Udemy Certification is awarded upon successful completion of a course.
• You must be able to code, simulate, and verify SystemVerilog Testbenches.

Syllabus:

• Verification Concepts Explained
• Introduction to System Verilog Language
• Basic SV TB - Connecting to your design
• SV - OOP concepts and Randomization
• Threads and Inter Process Communication
• Project Assignment - Building a Testbench for Ethernet Switch
• Introduction to Verification Methodologies