In this course, you will :
- Learn how to build thesA modern VLSI chip is a remarkably complex beast, with billions of transistors, millions of logic gates deployed for computation and control, large blocks of memory, and embedded blocks of pre-designed functions designed by third parties (referred to as "intellectual property" or IP blocks).
- How do people manage to create such complex chips? The answer is that a series of computer-aided design (CAD) tools takes an abstract description of the chip and refines it step by step to a final design.
- focuses on the major design tools used in the development of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC).
- Concentrate on key Boolean logic representations that allow you to synthesise and verify the gate-level logic in these designs.
1. Computational Boolean Algebra
- Computational Boolean Algebra: Boolean Difference
- Quantification Operators
- Application to Logic Network Repair
- Computational Boolean Algebra: Recursive Tautology
- Computational Boolean Algebra: Recursive Tautology—URP Implementation
2. Boolean Representation via BDDs and SAT
- BDD Basics
- BDD Sharing
- BDD Ordering
- Boolean Constraint Propagation (BCP) for SAT
- Using SAT for Logic
3. 2-Level Logic Synthesis, and Multi-Level Logic Synthesis via the Algebraic Model
- 2-Level Logic: The Reduce-Expand-Irredundant Optimization Loop
- 2-Level Logic: Details for One Step: Expand
- Multilevel Logic and the Boolean Network Model
- Algebraic Model for Factoring
- Algebraic Division
- Role of Kernels and Co-Kernels in Factoring
- Finding the Kernels
4. Multilevel Factor Extract and Don't Cares
- Mulitlevel Logic and Divisor Extraction—Multiple Cube Case
- Finding Prime Rectangles & Summary
- Implicit Don't Cares
- Satisfiability Don't Cares
- Controllability Don't Cares
- Observability Don't Cares