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In this course, you will :
- Unrestricted instructor assistance!
- The flow of Application Specific Integrated Circuit (ASIC) design and the fundamentals of ASIC design.
- Learn more than enough to begin designing real-world circuits with HDL.
- Have a firm grasp on how to write HDL code and how not to write it.
- The close connection between hardware and code.
- From the fundamentals to key principles for design engineers.
- A thorough examination of every line of code and piece of hardware.
Syllabus :
1. Introduction
- Review of VLSI concepts
- Quick CMOS basics (added as per request)
- What is VLSI?
- Review of terms
- Minimum feature size
- Why Integration?
- Broad areas in VLSI
- VLSI Design Styles - Full Custom
- VLSI Design Styles - Semi Custom
- VLSI Design Styles - FPGA
- VLSI Design Styles - Gate Array
- VLSI Design Styles - Comparison
- Full custom vs Semi custom
- ASIC vs FPGA
- ASIC Design Flow
- ASIC Design Flow - Design Specs
- ASIC Design Flow - Architecturing
- ASIC Design Flow - RTL coding
- ASIC Design Flow - Verification
- ASIC Design Flow - Synthesis
- ASIC Design Flow - Design for Testability
- ASIC Design Flow - Timing Analysis
- ASIC Design Flow - Floorplanning, Placement & Routing
- ASIC Design Flow - Formal Verification
- ASIC Design Flow - Power Estimation
- ASIC Design Flow - Fabrication
- ASIC Design Flow - Packaging
2. Verilog Basics
- Verilog Design Styles
- My First Dataflow Style Design
- My First Behavioral Style Design
- My First Structural Style Design
- 1-bit Full Adder (Sturctural-1)
- 1-bit Full Adder (Dataflow)
- 1-bit Full Adder (Behavioral)
- My first Test Bench
3. Designing Combinational Logic
- 4 Valued Logic
- Data Types
- Number Representation
- Bit and Bus
- Naming Conventions
- Operators - Bitwise
- Operators - Arithmetic
- Operators - Logical
- Operators - Relational
- Operators - Reduction
- Operators - Shift
- Operators - Concatenation
- Operators - Repetition
- Operators - Conditional
- Output Resolution Table
- 4-bit Full Adder (Structural)
- 4-bit Full Adder (Dataflow)
- 4-bit Full Adder (Behavioral)
- 4-bit Full Adder Test Bench
- 2:1 Multiplexer (Dataflow)
- 2:1 Multiplexer (Behavioral)
- 4:1 Multiplexer (Dataflow1)
- 4:1 Multiplexer (Behavioral)
- 2 X 4 Decoder (Dataflow)
- 2 X 4 Decoder (Behavioral)
- 3 X 8 Decoder (Dataflow)
- 4 X 2 Encoder (Dataflow)
- 4 X 2 Encoder (Behavioral)
- 4 X 2 Priority Encoder (Behavioral)
- 4 X 2 Priority Encoder (Dataflow)
- 4-bit Comparator (Dataflow 1)
- 4-bit Comparator (Behavioral)
- 8-bit Barrel Shifter (Combinational Left & Right)
- Designing Arithmetic & Logic Unit (ALU)
4. Designing Sequential Logic
- Clock, D-Latch and a D-Flip Flop
- D-Flip Flop vs D-Latch
- D-Latch (Dataflow)
- D-Latch (Behavioral)
- D-Latch with Asynchronous Reset (Behavioral)
- D-Flip Flop (Basic)
- Postitive Edge Triggered D-Flip Flop with Asynchronous Active High Reset
- Negative Edge Triggered D-Flip Flop with Asynchronous Active High Reset
- Postitive Edge Triggered D-Flip Flop with Asynchronous Active Low Reset
- Postitive Edge Triggered D-Flip Flop with Asynchronous Active High Set
- Synchronous D-Flip Flop with Active High Reset
- Synchronous D-Flip Flop with Active Low Reset
- Synchronous D-Flip Flop with Reset and Set
- Synchronous and Asynchronous Reset Design
- 8-bit Twin Register Set
- Designing a 5-bit Left to Right Shift Register
- Designing a 5-bit Universal Shift Register
- Designing a basic counter
- Writing a Test Bench for a Counter
- Designing an Up Counter with Load Option
- Designing an Up or Down Counter
- Designing a Modulus Counter
- Designing a Range Up Counter
- Designing a Range Up or Down Counter with Load Option
- Designing a Clock Frequency Divider (Divide by 2)
- Designing a Single Clock First In First Out (FIFO)
- Designing a Dual Clock First In First Out (FIFO)
5. Designing Memories
- Memory Array Options and Definitions
- Single Port Ram
- Dual Port Ram
- True Dual Port Ram
6. Designing Finite State Machines
- Mealy vs Moore Machine
- Mealy - 101 Non-Overlapping Sequence Detector
- Mealy - 101 Overlapping Sequence Detector
- Designing a Mealy Machine - Sequence Detector
- Moore - 101 Non-Overlapping Sequence Detector
- Moore - 101 Overlapping Sequence Detector
- Designing a Moore Machine - Sequence Detector
- Designing a Machine to Pick a Series of Coloured Balls and a Vending Machine
