Developing FPGA-accelerated cloud applications with SDAccel: Theory

Description

This course is designed for anyone interested in learning how to create FPGA-accelerated applications with SDAccel! 

We are entering an era in which technological advancement causes paradigm shifts in computing!
As a result of the tradeoff between the two extreme characteristics of GPP and ASIC, we can find a new concept, a new idea of computing... reconfigurable computing, which combines the benefits of both previous worlds. In this context, we can say that reconfigurable computing will have a broad, pervasive, and gradual impact on people's lives. As a result, it is time to focus on how reconfigurable computing and reconfigurable system design techniques can be used to build applications.

On the one hand, reconfigurable computing can perform better software implementations in terms of performance, but it comes at a cost in terms of time to implement. A reconfigurable device, on the other hand, can be used to design a system without requiring the same design time and complexity as a full custom solution while being outperformed in terms of performance.

Syllabus :

1. Familizarize youself with FPGA technologies

• Reconfigurable Computing and FPGA technologies
• FPGA-based systems and reconfiguration
• Programmable System-on-Multiple Chips
• Programmable System-on-Chips
• FPGAs main building blocks
• How to program an FPGA: bitstream and configuration
• How to program an FPGA: system description and physical design
• CAD Tools for FPGA-based systems design
• An introuction to the SDx development environment

 

2. A bird's eye view on SDAccel

• Hardware Design Flow
• An introduction to SDAccel and the OpenCL-based flow
• OpenCL computational model: global and local sizes
• Not only OpenCL! The Rationale behind the RTL and C flows
• SDAccel memory model
• SDAccel "emulations"
• SDAccel runtime

 

3. On how to optmize your system

• FPGA Parallelism vs Processor Architecture
• Scheduling, Pipelining, and Dataflow
• Application Optimization Flow

 

4. Optimize your system via SDAccel

• A bird's eye view on SDAccel optimizations
• Interface optimizations: Overall context and an overview of a typical target architecture
• Interface optimizations: a first example
• Burst data transfer
• Using full AXI data width
• Using multiple memory banks

 

5. Other optimizations

• Kernel optimization: loop unrolling
• Kernel optimization: loop pipelining
• Kernel optimization: array partitioning
• Host optimizations

 

6. An introduction to FPGA-augmented cloud infrastructures

• FPGA-enable cloud infrastructures
• An introduction to SDAccel and the AWS EC2 F1 instances
• Closing remarks and future directions

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