This course is for anyone interested in learning how a hardware component can be adapted at runtime to better respond to the needs of users and the environment. This adaptation can be provided by the designers or it can be a built-in feature of the system. FPGA technologies will be used to implement these runtime adaptable systems.
This course will provide a basic understanding of how FPGAs work and why they were chosen to implement a desired system.
The goal of this course is to teach everyone the fundamentals of FPGA-based reconfigurable computing systems. We cover the fundamentals of deciding whether or not to use an FPGA and, if this technology is proven to be the best option, how to programme it.
This is an introductory course designed to guide you through the FPGA world in order to make you more aware of the reasons why you might be willing to work with them and to provide you with a sense of the work you need to do in order to gain the benefits you seek by using these technologies.
We rely on some additional readings to provide additional information on the subject covered in this course.
Please keep in mind that most of these documents are provided through the IEEE Xplore Digital Library, which means that in order to access them, you must have a valid IEEE subscription, which you can obtain either directly from IEEE or through your university/company.
The course has no prerequisites and avoids all but the most basic mathematics. It presents technical topics through analogies, allowing even students with no technical background to gain a basic understanding of how an FPGA works.
One of the primary goals of this course is to democratise understanding and access to FPGA technologies. FPGAs are an excellent example of a powerful technology that can be applied in a variety of domains. The ultimate goal of this course is to be able to bring these technologies to domain experts and show them how FPGAs can help them improve their research. After completing this course, students will be prepared to take more advanced FPGA courses.
1. (A) A Bird's Eye View on Adaptive Computing Systems
- Course Introduction
- Reconfiguration in Everyday Life
- The Needs for Adaptation: an overview
- FPGA and reconfiguration: a 1st definition
- Runtime management
- Programmable System-on-Chip
- Programmable System-on-Multiple Chip
(B) An introduction to Reconfigurable Computing
- Reconfigurable Computing: a 1st definition
- Reconfigurable Computing: HW vs SW
- On how to improve the Reconfigurable computing performance via CAD improvements
- FPGA-Based Reconfigurable Computing
- System design space exploration and rationale behind partial reconfiguration
2. (A) Reconfigurable Computing and FPGAs
- Getting Familiar with FPGAs
- FPGA Basic Block: CLBs and IOBs
- FPGA Basic Block: Interconnections
- FPGA Configuration: an overview
- More Details on How To Configure and FPGA: the bitstream files
- Bitstream Composition
- Configuration Registers
- How to handle the complexity of an FPGA-based system
(B) Examples on how to configure an FPGA
- 4 inputs - 1 output OR LUT configuration example
- From the LUT to the CLB configuration example
- A simplified FPGA and its configuration settings
- An Example on how to implement a circuit on a simplified FPGA
- An Example on how to implement a circuit on a simplified FPGA: bitstram generation phase - CLBs
- An Example on how to implement a circuit on a simplified FPGA: bitstram generation phase - SBs and routing
3. (A) An Introduction to Reconfigurations
- A Common Vocabulary
- The 5 W's
- Reconfigurable Computing as an Exstension of HW/SW Codesing
- A Classification of SoC Reconfigurations
- A Classification of SoMC Reconfigurations
(B) Towards Partial Dynamic Reconfiguration and Complex FPGA-based systems
- Scenarios where Partial Reconfiguration can be effective
- How to use FPGA Reconfiguration to face area issues
- How to deal with the Reconfiguration runtime overhead
- Recurring modules to reuse them to reduce the Reconfiguration time
- Partial Reconfiguration to reduce the Reconfiguration runtime overhead
- Runtime management to explore alternative implementations
- Bitstreams relocation
- Bitstreams relocation and virtual homogeneity
4. (A) Design Flows
- Xilnx Design Flows through years
- Partial Reconfiguration Design Flows
- Xilinx Difference Based Partial Reconfiguration
- Xilinx Module Based Partial Reconfiguration
- Xilinx Partial Reconfiguration (PR) Flow
- Moudle Based vs Partial Reconfiguration Design Flows
- Rationale behind DRESD and the work done by the Politecnico di Milano
- From DRESD to CHANGE and ASAP, two new research initiatives from the Politecnico di Milano
- CAOS: from embedded to heterogeneous distributed FPGA-based computing systems
(B) Closing remarks and future directions
- We are working at the edge of the research in the area of reconfigurable computing. FPGA technologies are not used only as standalone solutions/platforms but are now included into cloud infrastructures. They are now used both to accelerate infrastructure/backend computations and exposed as-a-Service that can be used by anyone. Within this context we are facing the definition of new research opportunities and technologies improvements and the time cannot be better under this perspective. What it is needed now is new platform creation tools, monitoring and profiling infrastructure, better runtime management systems, static and dynamic workload partitioning, just to name a few possible areas of research. This module is concluding this course but posing interesting questions towards possible future research directions that may also point the students to other Coursera courses on FPGAs.